The use of advanced semiconductor manufacturing processes has enabled the reduction in semiconductor dimensions, and a corresponding increase in device operating speeds. These reductions, however, reduce the available cross-sectional area of interconnect regions, which leads to increased timing delays. To counteract this adverse consequence, various thin-film materials, such as metal silicides, may be formed atop doped polycrystalline silicon interconnects, which reduces the sheet resistivity of the interconnects and, thereby, reduces timing delays.
Conventional self-aligned silicide processes typically involve depositing a thin-film of metal and a protective cap on a semiconductor wafer and annealing to react the deposited metal with underlying silicon at various active regions. This annealing process forms a conductive silicide layer at various active regions. Metal deposited on insulators, such as oxides and nitrides, does not react during the annealing process and, therefore, is etched off (along with the cap) in one or more subsequent stripping operations. Connections may be subsequently formed utilizing one or more processing steps.
One undesirable consequence of these self-aligned silicide processes is the agglomeration of deposited metal during annealing stages, which in turn causes discontinuities. That is, at the elevated temperatures characteristic of annealing processes, and also of later middle of the line (MOL) processing steps, such as the deposition of a high-k dielectric or a metal fill for a replacement gate electrode, silicon within and/or underlying the deposited metal diffuses and eventually coalesces to form silicon grains and holes that break the continuity of the metalized silicide film. Accordingly, a narrow conductor constructed with agglomerated silicide tends to exhibit significant increases in average sheet resistance as the degree to which the metalized silicide film agglomerates and, therefore, causes discontinuities. Contacts formed above the film may punch or even fall through holes in the metalized silicide. Thus, in high speed circuit applications, agglomeration can result in performance degradation and even total functional failure. Accordingly, the adverse consequences of thin-film agglomeration are increasingly becoming one of the main yield detractors for semiconductor devices.
Conventionally, the sheet resistance of metal silicide layers has been measured inline with manufacturing processes to seek out resistivity variances and, thereby, the potential presence and degree of material discontinuities in these layers. Unfortunately, sheet resistance is influenced by many parameters, and therefore, electrical measurements of sheet resistivity do not directly quantify the presence or degree of these discontinuities.
A need, therefore, exists for methodology enabling efficient and accurate determination and monitoring of the effects of discontinuities during, or at least inline with, one or more semiconductor manufacturing processes. There exists a particular need for methodology enabling the characterization of thin-film discontinuities to facilitate the implementation of at least one countermeasure configured to increase the yield of semiconductor devices.